Phase-drift-compensation loop based on FPGA for energy-saving operation at booster ring of Taiwan Photon Source

Abstract

The RF system of the TPS booster ring was upgraded in 2018 with a digital low-level RF control system. Energy-saving operation in the top-up mode was also applied to the RF system at TPS booster ring. An unexpected phase jump occurred, however, which led to a failure, ramping the waveform of the gap voltage of the RF cavity. This large phase drift was caused by modulation of the klystron cathode current for energy-saving operation; sometimes it would trigger an interlock of the RF system. A large phase drift (from 82° to −4°) occurred while the cathode current was pulling high or low. The digital PID controller could not afford such large phase compensation. A phase-drift-compensation loop was implemented in the FPGA, operated with 1 kHz of a clock, which can provide ±1°/ms phase compensation. Through a combination of a PID controller and a phase-drift-compensation loop, the phase disturbance became stabilized. The maximum phase error of the gap voltage during energy-saving operation decreased from ±3.5° to ±0.7°. After applying the phase-drift-compensation loop, the cathode current of klystron can be set lower than before in an energy-saving period, which enables saving 60% power consumption compared with full-power operation.