Abstract
PEST is a CAD tool for implementing pseudo-exhaustive self test in integrated circuits. PEST's unique features are: 1. Parallel testing of all cones, 2. Global test point selection, and 3. A new cost effective scheme for test vector generation. AT&T's Network Interface Controller chip was designed using PEST. Effective 100% fault coverage without fault simulation or test generation was obtained with less than 24% transistor overhead. This paper begins with an overview of PEST's approach. The test generation algorithm is then described. Finally, the implementation of PEST in the Network Interface Controller is presented.
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