Abstract
The authors measured the relative permittivity of SiO2 deposited with a focused Ga+ ion beam by creating small parallel plate capacitors on a gold substrate. The relative permittivity of SiO2 ranged from a low of 7.5 to a high of 10.5 depending on the deposition yield, Y, defined as the film volume per ion dose. Lower Y led to the incorporation of metallic Ga0 clusters that increased the relative permittivity. The authors then used the SiO2 to create a parallel plate capacitor that acted as a capacitive delay in a 28 nm technology circuit to improve performance and timing marginality. The circuit segment in question had failed at an overvoltage of 106.1% of the nominal value, providing insufficient margin of operation and reliability. The addition of a 20 fF capacitor increased the upper limit of the performance margin from 106.1% to 108.5% of nominal supply voltage. The realized circuit edit provided conceptual confirmation that an additional delay in the clock signal would improve device performance as predicted by modeling.
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