Abstract
This paper is concerned with logic optimization of multilevel combinational logic circuits. In the light of theoretical work of the past years, where a circuit is modeled by a Boolean network in which each node implements a single-output Boolean function, we address how a concurrent optimization over multiple nodes or components can lead to further optimization compared to conventional minimization techniques. In particular, we provide a procedure for computing maximally compatible sets of permissible relations for multiple nodes. This is a generalization of the classical notion of a compatible set of permissible functions for a single node, where no method is known for correctly computing such a maximal set. We provide a method for computing the set correctly for the general case. Based on this, we develop and implement a procedure for optimizing multiple nodes concurrently. The proposed procedure has been implemented, and we present experimental results.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
