Periodic learning-based region selection for energy-efficient MLC STT-RAM cache

Abstract

The emerging multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) is becoming one of the most promising candidates to replace SRAM as on-chip last-level caches. Compared with single-level cell (SLC) STT-RAM design, MLC cache outperforms SLC cache in terms of storage capacity. However, due to the cell design constrains, MLC STT-RAM suffers from considerably long write latency and high write energy. To explore the potential benefits of MLC STT-RAM cache, this paper proposes a scheme named periodic learning-based region selection (PLRS). We first formulate the region selection problem with greedy algorithm and then profile and collect the cache access behavior through periodic learning. Finally, PLRS will determine region selection based on the behavior information. The experimental results show that PLRS reduces dynamic energy consumption by 22.7% and reduces execution time by 16.2% on average compared to conventional MLC STT-RAM, with negligible overhead.