Abstract
In this work, the influence of interface trap charges (ITCs) on electrical parameters of gate stacked heterojunction silicon on insulator Tunnel FET (GSHJ-SOITFET) and GSHJ-TFET on SELBOX substrate (GSHJ-STFET) is investigated using TCAD simulator. Here, two types of trap distributions like Uniform and Gaussian are considered at Silicon/gate oxide interface. The influence of ITCs on transfer characteristic, electron density, energy band diagram (ON, OFF and Ambipolar states), transconductance (gm), and cut-off frequency (ft) are highlighted for these two structures. Moreover, the linearity parameters are highlighted in the presence of ITCs of these structures. It is seen that DC, RF/analog, and linearity characteristics of GSHJ-STFET are immune to ITCs compared to GSHJ-SOITFET. Also, GSHJ-STFET has improved electrical behavior than GSHJ-SOITFET. The proposed fabrication processing steps of GSHJ-STFET is also highlighted in this work. Finally, a comparative study of electrical parameters for GSHJ-STFET with the existing literature is highlighted.
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