Performance-driven placement for design of rotation and right arithmetic shifters in monolithic 3D ICs

Abstract

Recent advances in three-dimensional integrated circuits (3D-ICs) offer a new dimension of design exploration at traditional physical architecture of datapath components. The emerging monolithic inter-tier vias (MIVs) provides more advantages over through-silicon vias (TSVs) in terms of higher integration density and lower design overhead. In this work, we develop a performance-driven framework which uses simulated annealing to produce gate-level 3D placement layout for rotation shifter and right arithmetic shifter design. Compared to the optimum 2D layout, the critical path of our solution is much shorter with limited overhead on total wirelength. Our work indicates that by gatelevel 3D-IC integration, the new physical dimension can be well leveraged with improvement on both performance and power of shifter design.