Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks

Abstract

Random Delay Insertion (RDI) has been shown to be an effective countermeasure to side-channel attacks (SCAs) on on-chip power networks. RDI effectively reduces the correlation between the power dissipation and the processed data. However, random delay insertion can degrade circuit performance. Considering the theoretical benefits of delay insertion, this paper proposes a novel methodology that adds delay to interconnect buses to mitigate electromagnetic (EM) SCAs without degrading bus latency. The methodology comprises an efficient delay insertion scheme that hinders electromagnetic attacks, where the delay is inserted into the boundary lines of the bus. As the worst-case bus latency is determined by the lines that drive the maximum cross-coupling capacitance, inserting delay at the boundary lines does not affect the circuit performance as these lines always drive a lower capacitance. The inserted delay improves the security strength of the bus to EM attacks due to the reduction of the correlation between EM emissions and transmitted data, making the methodology effective and directly applicable with negligible overhead. The technique is applied to interposer based off-chip memory buses due to the increasing adoption of 2.5-D integrated systems (although the method is effectively applicable to any interconnect bus). Simulation results show that the technique decreases SNR below 1, which makes EM attacks unsuccessful, and does not increase the (worst-case) bus latency, sustaining the overall circuit performance. Consequently, the proposed method provides a superior EM SCA mitigation method compared to the state-of-the-art. Indeed, theoretical analysis and simulation results demonstrate that the new technique can offer the same level of protection against SCAs with better performance than other hardware RDI countermeasures.