Performance study of a clustered shared-memory multiprocessor

Abstract

A shared-memory multiprocessor having clusters of processing elements and memory modules is considered. Each cluster has two others as its neighbors. The clusters are interconnected in such a way that the memory modules of a cluster can also be accessed by the processors of the neighboring clusters besides its own processors through its cluster interconnection network. The processors and memories of all clusters are also connected to a shared interconnection network. This permits processors to access memory modules of the non-neighboring clusters. Generalized multistage interconnection networks are used for both types of connections. The time required to access memory modules is reduced by scheduling tasks sharing large data with each other on neighboring clusters or on the same cluster thereby providing for memory access a low latency path through the cluster interconnection network. The time to access memory modules of the non-neighboring clusters also reduces due to reduced contention and because of fewer requests going through the shared interconnection network. Since the memory modules of a cluster are the main memory modules, an additional level of cluster memory is not required. This alleviates the data coherence problem. A Markov chain model is used to study the performance of this multiprocessor under circuit switching. Considerable improvement in performance over a simple shared memory multiprocessor using multistage interconnection network is observed. The model is extended to study the effects of synchronized memory access to shared data.