Abstract
The performance potential of silicon bipolar transistors is investigated by device simulation. Using a one-dimensional drift-diffusion equation solver, the SPICE parameters of selfaligned transistors are extracted from doping profiles and device geometries. These parameters are used to predict the CML gate delay for different doping profiles. The validity of this extraction procedure is verified by comparison with experimental data. For a double-diffusion type doping profile with a pinch resistance of 15kΩ/□, a transit frequency of 56GHz and a CML gate delay of ∼15ps are achievable. With a doping profile including a low-doped emitter region and a high base doping concentration, significant improvements are found: A transit frequency of 81.6GHz and a pinch resistance of 10kΩ/□ enable CML gate delay times below 10 ps.
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