Abstract
The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.
Highlights
Semiconductor technologies are in a constant innovation race to create a new functionality and meet growth-up expectations
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) can’t no longer comply with Moore’s Law [2,3], which led to the need of finding alternative technologies
Because the complete adder circuit is indispensable in any digital product, the performance of any digital circuit can be improved by enhancing it performance
Summary
Semiconductor technologies are in a constant innovation race to create a new functionality and meet growth-up expectations. Efforts to optimize performance are continuous, efforts such as the Conventional–Complementary Metal Oxide Semiconductor [1], the Removed Single Driving Full Adder (RSD-FA) [6], the Hybrid Pass Transistor Logic with Static CMOS output drive (HPSC) [3], the 18 Transistor 1-bit Full Adder [7], the Hybrid Multi-Threshold Full Adder (HMTFA) [8], and the low power based CNTFET [9] The implementation of these adder circuits takes place using various logic families, the above mentioned adders have different advantages and disadvantages.
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