Performance monitor unit design for an AXI-based multi-core SoC platform

Abstract

As the physical gate-count in System-On-Chip (SOC) system increases and system design complexity grows steadily, it becomes more and more difficult to achieve good resource utilization by assigning each task to certain hardware IP and tracing the execution patterns of each task efficiently. Therefore, the performance monitoring feature is getting more and more important to provide the ease of system monitoring and performance debugging. In this paper, we present a performance monitoring unit (PMU) for the AMBA Advanced eXtensible Interface (AXI) bus. The PMU has capability to measure major performance metrics, such as bus latency for the specific master requests and amount of memory traffic for specific durations. It can also measure the contention of the bus masters and slaves in the SOC. We present the distributor and the synchronization method to use multiple performance counting units as well. The performance monitoring unit has been verified in the platform FPGA board with 9 by 4 AXI interconnect configuration. These monitoring features can give the insight to system design architect by helping to find and analyze the performance bottleneck of target system.