Highly Reconfigurable Performance Monitoring Unit on RISC-V

Abstract

A high reconfigurable performance monitoring unit (PMU) structure is proposed and implemented to monitor and analyze processor events and tasks. In this paper1, the traditional PMU based on RISC-V is improved, so that the performance monitoring counter can be configured with any number of slave configuration registers by instructions, which improves the flexibility of function. The function of slave configuration register is developed to enrich the monitoring function and information. This paper also improves the traditional working mode of PMU, and realizes the additional working mode of PMU “general register mode” by using the existing performance monitoring resources, so that the CPU can directly use the additional general register resources. Moreover, PMU also adds the “low power consumption mode” to reduce its power consumption. In this paper, HDL is used to implement the module, and it is applied to RISC-V processor SCR1 system to run benchmarks as Dhrystone and Coremark for experimental verification. This PMU structure can also be applied to other instruction set architecture for processor systems and multicore systems.