Performance evaluation of Sigma Delta Zero Crossing DPLL

Abstract

The objective of this work is to evaluate the performance of the Sigma — Delta first order Zero Crossing Digital Phase Locked Loop (SD-ZCDPLL) and compared with the conventional ZCDPLL in the absence and presence of noise. A one bit sigma-delta modulator is used as a part of the proposed structure. The analysis and evaluation of the proposed SD-ZCDPLL has shown to give improvement in the locking range and loop jitter when compared to the conventional ZCDPLL. The Digital Controlled Oscillator (DCO) of the proposed SD-ZCDPLL is controlled based on the input frequency deviation of the input signal. For fine tuning, the DCO is controlled through the standard tracking process of the conventional ZCDPLL. While for coarse tuning, the one bit Sigma-Delta modulator path is activated through a Finite State Machine (FSM) to control the DCO. Through this dual tuning process, the SD-ZCDPLL performance has been improved.