Performance Evaluation of Low Power Hybrid Combinational Circuits using Memristor

Abstract

Recently, extending the use of memristor technology from memory to computing has received a lot of attention. Memristor-based logic design is a new concept that aims to make computing systems more efficient. Several logic families have emerged, each with its own set of characteristics. In this paper, CMOS-based hybrid memristor-based combinational circuits are designed. Many computational devices require combinational circuits. All of the proposed designs were analysed for power, latency, and transistor count. Cadence Virtuoso is used for simulation of circuits. In this study, we used the VTEAM model to describe the simulated memristor because it is easy to understand and gives accurate results.