Low Power Linear Feedback Shift Register Using DY-CML

Abstract

A Linear Feedback Shift Register (LFSR) is a sequential shift register that cycles through a succession of binary values in a pseudo-random way using combinational logic. Pseudo-noise sequences, whitening sequences, and fast digital counters are some of the applications of LFSR. The design of a 4-bit LFSR employing CMOS, MOS Current-Mode Logic (MCML), and Dynamic Current-Mode Logic (DY-CML) approaches are shown in this paper. MCML has low power consumption and better performance. The disadvantage of MCML approach is that it has more static power dissipation due to the constant current source. In order to solve the issues of MCML approach, the DY-CML with a dynamic current source is used to design the LFSR. All designs are simulated using the Mentor graphics tool, which uses 90nm technology. This paper also includes a comparison of LFSR’s in terms of power, delay, and transistor count.