Performance evaluation of load/store issue and memory access policies

Abstract

Six load/store issue and memory access policies are studied for improving the instructions per clock (IPC) of current superscalar processors. Experiments using instruction‐driven simulation were used to demonstrate the performance potential of these methods. The three key factors in rank to improve the IPC are found to be: (1) allowing a load issue to bypass an un‐issued store and an uncommitted store, (2) de‐coupling the store‐value from the store‐address for store issue, and (3) constraining the speculative load accesses in the load buffer until the preceding store addresses are known. The most effective issue policy is to allow a load to bypass un‐issued stores, decouple the store‐value from store address, and constrain the speculative load accesses in the load buffer until the preceding store addresses are known. This paper also explored mechanisms to avoid deadlocks for the cases where the load/store buffer slots are not allocated at the time the reservation stations are allocated. Examples are used to show how the deadlocks occur and the means to prevent them.