Pipeline controller on dynamic memory access policy

Abstract

This paper presents a novel pipeline memory controller based on multi-core network processing. This pipeline controller includes six level pipeline operations which can reduce access latency and provide bank and row address relationship of two adjacent instructions in advance. The controller would take a dynamic memory access policy according to the address relationship got from the pipelines operations. The traditional memory controller usually takes a static memory access policy which is applicable to only bank interleaving optimization or page hit optimization. Unlike the traditional controller, the pipeline controller could take both bank interleaving and page hit optimization in the same memory system under the dynamic access policy — Open Page (OP) or Close Page Autoprecharge (CPA)[1]. The performance analysis shows that this pipeline memory controller can reduce memory access latency and the improved the throughput greatly when compared with traditional memory controller.