Performance evaluation of high speed compressors for high speed multipliers using 90nm technology

Abstract

This paper describes high speed compressors for high speed parallel addition multipliers like Booth Multiplier, Wallace Tree Multiplier in Digital Signal Processing (DSP). We proposed 4-3, 5-3, 6-3 and 7-3 compressors for high speed multiplication. The compressors reduce vertical critical path more rapidly than conventional compressors. A 5-3 conventional compressor can take four steps to reduce bits from 5 to 3, in the case of proposed it takes only 3 steps. All the compressors are designed with half adder and full Adders. These compressors are simulated with T-Spice at a temperature of 25°C with fixed frequency of 10MHz at 2.0V and 1.0Vwith 90nm MOSIS technology. The Power Delay Product (PDP) of these compressors calculated to analyze the delay and energy consumption.