Design of Wallace Tree Multiplier Using Sparse Kogge-Stone and Brent–Kung Adders

Abstract

In many digital signal processors and different applications, the massive role is played by the multiplier. In any VLSI design mainly power, area and speed play a massive role, by improving any of these parameters the overall performance will be improved. Array multipliers and Tree multipliers are various types of multipliers, among those Wallace tree multiplier belongs to Tree multiplier which is better than booth multiplier in terms of speed, area, design complexity. Different existing approaches had been developed for the reduction of partial products. One of the existing approaches uses full adders and half adders in Wallace tree multiplier, but by using this approach number of stages would be increased when higher order multiplication is considered. To overcome this, an approach is proposed which includes 4:2 compressors & parallel prefix adders in Wallace tree multiplier design.