Abstract

This paper presents a hierarchical approach to link the advanced multisubband Boltzmann transport equation (MSBTE) solver to the conventional drift-diffusion (DD) model for performance evaluation of non-planar transistors in logic technology development. An automated, physics-based procedure to extract the DD model parameter set from the MSBTE simulation is described. An update on the surface roughness scattering model valid for finite barriers is also shown. As an application, the MSBTE to DD calibration is performed for a silicon nanowire transistor. The calibrated parameter set is applied to a dual channel nanowire transistor, and the effects of the source/drain series and contact resistances are studied.

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