Performance Evaluation of FFT through Adaptive Hold Logic (AHL) Booth Multiplier

Abstract

Multiplication is such a key operator in any kind of signal processing modules. Processor’s performance is potential, if the processing elements like multipliers or adders are efficient. One of the stringent multiplier is through Booth’s multiplication algorithm which takes 2’s complement notation of two signed binary numbers. It reduces the number of steps while doing addition when compared with normal multiplication. About radix-8 Booth multipliers’ fundamental design, this is tested on ASIC-based platforms. FPGA-based hardware accelerators cannot give the required performance gain. This can be achieved by using FPGAs and ASICs. For approximation 6-input Look Up Table (LUT) and carry chains of the FPGAs are used. In the existing method, it is possible to have data with 40% of error probability reduction and is not acceptable in logic design for signal processing or for data communications. To overcome this error in end product, instead of Booth multiplier, AHL (Adaptive Hold Logic) Booth multiplier is recommended. With the AHL booth multiplier, the error Probability is expected to reduce to a great extent. Means that100% of accurate data reception is possible at the output compared to existing approximate Booth multiplier. AHL Booth multiplier improves the operation speed and reduces the delay. To test its impact, FFT will be designed with and without AHL Booth multiplier and is simulated using Xilinx ISE. Area, delay and power dissipation parameters of FFT are compared for an effective logic realization.