Performance evaluation of delay testable enhanced scan flip-flop

Abstract

Delay faults are regularly encountered in nanometric regime that’s why it is very important to detect these faults during the manufacturing test. Testing of delay fault requires two test vectors. In general delay faults are tested using scan-based designs. The second test vector is generated in scan either by broadside test (launch of capture test) or by skewed load test (launch-on-shift). Broadside test is preferred over skewed load test approach in designs because it is implemented by system clock for scan operations while skewed load delay test requires fast scan enable signal which is not supported by most of designs but skewed load delay test provides better transition delay fault coverage with fewer test patterns compared to broadside delay test. For maximum detection of delay faults it is essential that vectors in the pair should be independent. Due to structural limitation of scan independent test vector can’t be applied to the design, which results in degradation of delay test coverage. However this can be accomplished by the use of enhance scan flip-flop which presents the application of independent delay test vector pair at the cost of high area overhead and also requires fast hold signal, similar to scan enable signal in case of skewed load testing. This paper presents a new enhanced scan flip-flop design implemented with slow hold signal and we also discussed the performance penalty caused by the delay testable enhance scan flip-flop. Experimental results shows improvement in transition delay fault coverage on ISCAS 89 benchmark circuit with this method.