Performance evaluation of 3-D stacked 32-bit parallel multipliers

Abstract

Conventional two-dimensional (2-D) implementation technologies face certain limitations; to overcome these limitations, three-dimensional (3-D) integration technologies have been developed. There has been a focus on circuit partitioning strategies because they play an important role in exploiting the potential of 3-D stacked circuits. The Middle-Grain circuit partitioning strategy has been proposed to exploit the potential of 3-D stacked circuits. The proposed strategy equalizes the area of each layer and avoids the critical paths across different layers as much as possible. In this study, 3-D stacked parallel multipliers are designed using various circuit partitioning strategies. Experimental results demonstrate that the 3-D stacked 32-bit parallel multiplier, designed using the proposed strategy, achieves a 27% delay reduction as compared to the 2-D implementation.