Performance evaluation and design considerations of 2D semiconductor based FETs for sub-10 nm VLSI

Abstract

Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using non-equilibrium Green's function (NEGF) formalism are performed to rigorously evaluate the scalability and performance of monolayer/multilayer 2D semiconductor based FETs for sub-10 nm node VLSI technologies. Device design considerations in terms of the choice of prospective 2D materials/structure/technology to fulfill the sub-10 nm ITRS requirements are analyzed for the first time. Firstly, it is found that MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs can meet high-performance (HP) requirement up to 6.6 nm node by employing bilayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as the channel material, while low-standby-power (LSTP) requirements present significant challenges for all sub-10 nm nodes. Secondly, by studying the effects of underlap (UL) FET structures, scattering strength and carrier effective mass, it is found that the high mobility and suitably low effective mass of tungsten diselenide (WSe2), aided by UL, enable 2D FETs for both HP and LSTP applications at the smallest foreseeable (5.9 nm) node. Finally, possible solutions for sub-5 nm nodes are also proposed based on the effects of critical parameters on device performance.