Performance enhancement of slot synchronization in W-CDMA

Abstract

The W-CDMA system plays an important role in the 3G cellular systems because of its compatible networking architecture to the present popular Global System for Mobile Communications (GSM) systems as well as the salient features of a Code Division Multiple Access (CDMA) system, including multi-path fading tolerance, high system capacity, low power consumption, good performance and coverage. In CDMA system, a procedure used by a Mobile Station (MS) to search for the best cell site and achieve code, time, and frequency synchronization with it is referred as cell search. Fast cell search is essential to reduce switch on delay (initial cell search), increase stand by time (idle mode search) and maintain good link quality (active-mode search). This is particularly true for the Wideband Code Division Multiple Access-Frequency Division Duplex (W-CDMA-FDD) system since it employs nonsynchronous base stations instead of synchronous ones of other CDMA systems to extend coverage from outdoor to indoor. Cell search is critical for achieving code and time synchronization. The main process of achieving cell search is divided into three stages followed by code verification, tracking and carrier frequency adjustment: 1) slot synchronization, 2) frame synchronization and code group identification, 3) primary scrambling code identification. This paper addresses slot synchronization in downlink as cell search algorithm in W-CDMA. In the three step search, the receiver searches for the slot timing by correlating the received signal with the Primary Synchronization (PSCH) code using Matched Filter (MF). This paper propose a design for a hierarchical matched filter for Primary Synchronization Code (PSC). The aim is to reduce the hardware complexity using Field Programmable Gate Array (FPGA) logic resources required to realize the filter.