Performance enhancement of FINFET and CNTFET at different node technologies

Abstract

Developing technologies need smaller and faster IC's, hence transistor size has to be scaled down. In order to satisfy this, transistor size in a chip has been decreased drastically from micro range to nano-range. MOSFET was the mass element in any IC at micro size, but when scaled down to nano regime performance degrades because of short channel effects. It is shown here that the FinFET, which gives the better performance and scalability, will replace it. However in 14 nm node and beyond, FinFET also has certain disadvantages; hence some performance enhancement techniques have been introduced to yield good results in 14 nm node. Such techniques include changing the channel materials, use of high-K gate dielectric, etc. We used parameters defined in ITRS update 2013 to simulate FinFET in 14 nm node and we adapted various techniques. Finally the performance enhancement of both finFET and CNTFET for 14 nm node is shown.