Performance Enhancement of Caches in TCMPs Using Near Vicinity Prefetcher

Abstract

Prefetching aids in reducing the increasing processor-memory latency gap in a multiprocessor system. In a Tiled Chip MultiProcessor system (TCMP), the cache block reuse pattern of applications vary across the cores. Applications that have a working set larger than the L1 cache size cannot be accommodated in the limited L1 cache space. Such applications suffer from cache space constraints. Prefetching cache blocks of heavy application may cause thrashing by evicting useful cache lines from L1 cache thereby demanding frequent cache block replacements. On the other hand, light applications due to less cache block demands may under-utilize the available L1 cache space. This paper proposes Near Vicinity Prefetching (NVP) where some prefetch blocks are placed in the L1 caches of adjacent tiles running light applications. The prefetching framework works simultaneously with other L1 caches in different tiles to reduce the cache block access time. During cache hits in the neighboring L1 cache, the network transaction required to bring that block reduces from an average of 'n' hops to just one. NVP helps in better cache space utilization and reduced network transactions at minimal hardware. Experimental analysis on a 64-core TCMP with SPEC CPU 2006 benchmark mixes shows that the average memory access time is reduced by 4.42% using the proposed NVP technique.