Performance enhancement of 1.7 kV MOSFET using PIN-junction gate and integrated heterojunction

Abstract

A novel PIN-junction gate 4H-SiC UMOSFET with integrated heterojunction (PJG-UMOSFET) is proposed and numerically studied. The integrated heterojunction diode effectively suppresses the conduction of the intrinsic PN diode in the reverse conduction state of PJG-UMOSFET. The device simulation results show that the on-resistance (Ron) of the device is reduced by about 20.5 % compared with the traditional SiC UMOSFET, and there is almost no specific conduction resistance decrease. The reverse recovery time (tπ) and reverse recovery charge (Qπ) are reduced by 42.1 % and 68.4 %, and the gate-to-drain charge is reduced by 41.2 %. In addition, a feasible manufacturing process method for the proposed device is provided.