Performance-driven scaling of BiCMOS technology

Abstract

A BiCMOS scaling analysis is carried out to optimize the performance of digital BiCMOS gates while accounting for the conditions that make the direct application of conventional BJT and MOS scaling rules invalid. A simple set of technological parameters that directly affect BJT and MOS device characteristics in the context of BiCMOS is identified. Scaling of the technological parameters leads to scaling of the device parameters which in turn appear in a comprehensive, accurate delay model. The scaling of logic gate delay under various possible scenarios is investigated and a set of optimal scaling rules is proposed that simultaneously scales all components of gate delay. The optimal rules require a linear reduction in horizontal and vertical dimensions, a linear increase in collector doping, and a square root reduction in supply voltage. When 1 mu m, 5 V, 8 GHz technology is scaled to 0.5 mu m, 3.5 V, 18 GHz according to the optimal scaling rules, a 2* improvement in BiCMOS performance is obtained. Despite the supply voltage reduction BiCMOS maintains a performance advantage of 1.5* over CMOS. >