Figures of Merit to Characterize the Importance of On-Chip Inductance in Single Lines

Abstract

Listen

Translate article

It has become well accepted that interconnect delay dominates gate delay in current deep submicrometer digital integrated circuits [3]-[5]. With the continuous scaling of technology and increased die area, this situation is expected to become worse. In order to properly design complex circuits, more accurate interconnect models and signal propagation characterization are required. Historically, interconnect has been modeled as a single lumped capacitance in the analysis of the performance of on-chip interconnects. With the scaling of technology and increased chip sizes, the cross-sectional area of wires has been scaled down while interconnect length has increased. The resistance of the interconnect has therefore become significant, requiring the use of more accurate RC delay models. At first, interconnect was modeled as a lumped RC circuit. To further improve accuracy, the interconnect has been modeled as a distributed RC circuit (multiple T or П sections) for those nets requiring more accurate delay models. A well known method used to determine which nets require more accurate delay models is to compare the driver resistance R tr and the load capacitance C L to the total resistance and capacitance of the interconnect line, R t and C t [25], [35]. Typically, those nets that require more accurate RC models are longer, more highly resistive nets.