Performance Demonstration of HVDC Circuit Breakers

Abstract

This paper provides an overview of the complete research and development track that led to the public demonstration of three HVDC circuit breaker (CB) technologies rated up to 350 kV, 20 kA. The lessons learned are used as inputs to the international standardization activities related with the testing of HVDC CBs. Since HVDC grids are almost completely non-existent, a model of a conceptual HVDC grid is used to study the impact of faults on such grids. By embedding realistic models of HVDC CBs, this study is used to quantify the electrical stresses to which the HVDC CBs are subjected. Next, a detailed set of test requirements is set up, consisting of clearly defined test-duties, to qualify the breaker for its main task – fault current interruption under full power condition. These test requirements are agreed among the manufacturers of the three technologies of HVDC CBs. In addition, a study evaluating the practical aspects as well as comparing the performance of possible test circuits singled out the test circuit based on low-frequency AC short-circuit generators as technically the best option to replicate the stresses as in service, quantified by a number of essential phases in the interruption process.