Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node

Abstract

Applications of stress/strain are now part of technology ‘boosters’ in microelectronics industry among other technologies such as silicon-on-insulator or the metal gate/high-k techniques. Application of strain in channel significantly increases carrier mobility. Thus, there is a need to characterize the deformations at nanoscale in the semiconductor induced by the strain. Uniaxial compressive strain has been an indispensable performance booster for p-channel FinFETs. In this work, based on extensive 3D process and device simulations with mechanical stress simulations using finite element techniques, performance assessment of nanoscale tri-gate FinFETs with uniaxially strained-SiGe channel (fin) has been presented. A comprehensive study based on stress tuning parameters is carried out to investigate the possible highest amount of process induced stress transfer to SiGe fin for optimization of device performance. The impact of process-induced strain on carrier mobility enhancement in 7 nm technology node is another major focus of this study. The stress transfer efficiency is shown for different process conditions with different Ge content. Technology CAD simulations show that strain in the fin is larger for higher Ge contents in the SiGe layer for p-channel FinFETs. For the first time, conversion from biaxial compressive strain of SiGe to uniaxial compressive strain in SiGe layers via process simulation has been demonstrated and implemented in the virtual fabrication of uniaxially strained-SiGe channel (fin) tri-gate FinFETs. A detailed performance comparison has been performed with conventional bulk-Si tri-gate FinFETs.