Performance comparison of software and FPGA implementation of computationally intensive algorithms

Abstract

Fast Fourier Transforms (FFT) based digital signal processing has vast applications in radar signal processing. FFT can be performed using a general purpose computer or a specially designed digital hardware. It is important to analyze the performance of such computationally intensive algorithms in hardware (FPGA) and software implementation in single processor machines. For years the common practice for implementing FFTs (in hardware other than application specific integrated circuits (ASIC)) has been to run them on a digital signal processor. But as FPGAs have evolved and have begun to accommodate function specific computing cores, FPGAs are beginning to displace digital signal processors as the optimum FFT solution. In this paper the implementation of FFT radix 2 algorithms in C++ and design of parameterized floating point FFT in FPGA is discussed. The VERILOG design is tested using the Modelsim simulator and is synthesized in Xilinx ISE