Performance analysis of network-on-chip in many-core processors

Abstract

Network-on-chip (NoC) is an integral part of many-core microprocessors. Performance analysis of network-on-chip directly affects the performance of the microprocessor. In this paper we propose a mathematical model to represent packet flow in an NoC as an open feed-forward queuing network. We study the performance of NoC by varying different parameters that includes packet injection rate, packet size, buffer size and number of virtual channels. We also discuss how different flow control algorithms, injection processes, traffic patterns can be incorporated in our model. Apart from the speedup achieved by our model, we also demonstrate that our model can be used to explore various configurations of NoC with minimal error.