Abstract
This paper examines the implementation of a retinal vessel tree extraction technique on different hardware platforms and architectures. Retinal vessel tree extraction is a representative application of those found in the domain of medical image processing. The low signal-to-noise ratio of the images leads to a large amount of low-level tasks in order to meet the accuracy requirements. In some applications, this might compromise computing speed. This paper is focused on the assessment of the performance of a retinal vessel tree extraction method on different hardware platforms. In particular, the retinal vessel tree extraction method is mapped onto a massively parallel SIMD (MP-SIMD) chip, a massively parallel processor array (MPPA) and onto an field-programmable gate arrays (FPGA).
Highlights
Nowadays, medical experts have to deal with a huge volume of information hidden in medical images
Among the plethora of different platforms that today offer hardware reconfigurability, this paper focuses on the suitability of field- programmable gate arrays (FPGAs) and massively parallel processor arrays (MPPA) for computer vision
Even with a high-end computer, the result is not satisfactory in terms of speed. Candidate systems using this algorithm require a faster response. To address this and other problems associated with a conventional PC, such as size or power consumption, we propose three implementations on three specific image-processing devices: a Vision Chip, a custom architecture on FPGA and a MPPA
Summary
Medical experts have to deal with a huge volume of information hidden in medical images. During the guiding forces extraction step, a directional gradient is calculated from the global potential field As this is a non-binary image, a thresholding operation is needed to obtain the pixels to which the contour will evolve. Candidate systems using this algorithm require a faster response To address this and other problems associated with a conventional PC, such as size or power consumption, we propose three implementations on three specific image-processing devices: a Vision Chip, a custom architecture on FPGA and a MPPA. The great flexibility of the network, which includes a deep hierarchy where each level is optimized for certain tasks, made them very appropriate in all industrial fields and research areas It is one of its drawbacks because much of the chip area is consumed in connections that are not always necessary, increasing cost and power consumption and reducing the working frequency. Accuracy can be tuned to the real needs of the application, saving resources
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