Performance analysis of indium phosphide channel based sub-10 nm double gate spin field effect transistor

Abstract

In this paper, a novel double gate Spin-Field Effect Transistor (DG spin-FET) with indium phosphide (InP) as channel material is evaluated. The proposed spin-FET device is well suited for CMOS technology, as both n and p-type devices can be formed by using parallel and anti-parallel combinations of spin-FET respectively. The proposed device feature size is in sub 10 nm range and therefore is compatible with state of the art integrated circuit technology. The leakage currents have been reduced by employing high-k dielectric (HfO2). A comparative analysis of the proposed device with the devices reported in the literature confirm that the proposed device has improved on-off ratio and ON current. Besides the device has low transit time and less parasitic capacitances required for high frequency and low power applications respectively.