Performance analysis of High Speed ADC using SR F/F

Abstract

This paper present a new design of comparator for flash ADC . The flash ADC is the fastest Application ADC that requires the high speed comparator. The new design consist of sense amplifier and SR Latch ,the combining configuration of design have the considerable stable output which helps in high speed and resolution. The use of SR symmetric latch makes stable output as compared to the conventional SR latch moreover the design has high resolution. This paper has been done in 180 nm and 90nm gpdk in CADENCE VIRTUOSO. For low power application. There are many issues in the design of the comparator, we will discuss those design issues in this paper. I. Introduction The design of comparator is the most critical part in the flash ADC, since the speed and the resolution is determined by the comparator. The dual tail current sense amplifier based comparator can run faster with lower supply voltage than the normal one, and the kick back effect is also better than the normal one. The symmetric S-R latch provides shorter delay time and stable time than the normal S-R latch. Combing the sense amplifier based comparator and the symmetric S-R latch, the whole block can run faster and the output signal is more stable than the normal structure. This design of comparator is for 2GSample/sec flash ADC. Based on IEEE 802.15.3a WPAN UWB applications, the signals using multi-band orthogonal frequency division multiplexing (MB-OFDM) occupy a bandwidth of 528MHz for every band. It requires the conversion rate at least higher than 1.06GSample/sec. 1.1. The Analysis Of The Traditional Sense Amplifier Based Comparator And Sr Latch: In the analysis of any comparator there are 2 stages in which operation is divided, one is reset phase and other is regeneration phase. In this sense amplifier based comparator sense amplifier connects positive feedback with the resistive input as shown in fig.1.Now during reset phase when clock is low, the nodes of inverters (M1-M4) are charged to Vdd, through transistor M7 and M8. Again on regeneration phase when clock is high Nmos transistor M9 is turned on which is a part of differential pair M5 and M6. Current flowing through this pair controls the latch circuit and small changes between differential pair cause large output change. And this differential pair discharge the node Ni, and later difference of the input voltage will built charge it. When Ni come to Vth voltage then inverter M1,M3 turns on and this wil start the positive feedback. After Ni comes to 2Vth below Vdd transistor M2,M4 are turn on. Now with the help of strong positive feedback small input converted to full differential output. For the generation of output there is very short period of time in sense amplifier when its gain is good.so switch M11 ,M12 is added to increase the integration time. In the conventional sense amplifier, it is better to add a reset switch (M11, M12) connecting the Vdd and the Di so as to increase the integration time . In the sense amplifier there is only a very short time in which the differential pair actually have the gain. Actually the differential pair comes to triode region during Ni drop to Vth. This reset transistor also increase the active time of differential pair and decrease the offset effect in coming signals.