Abstract

A novel model for the performance evaluation of finite-buffered multistage interconnection networks (MINs) is proposed. In contrast to previous models, which are either rather inaccurate when input load is high or only applicable to some special cases (e.g., infinite buffers, single buffers, or low input load), the proposed model is very accurate for all ranges of input load and allows switching elements and buffer modules to be of any arbitrary sizes. By carefully redefining the states, the authors take into account the dependency between packets in consecutive clock cycles and states of buffers in adjacent stages so that the analysis can be more accurately performed. >

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.