Abstract

Abstract : In recent years, as a result of advancing VLSI technology, Orthogonal Frequency Division Multiplexing (OFDM) has received a great deal of attention and has been adopted in many new generation wideband data communication systems such as IEEE 802.11a, IEEE 802.16e, HiPerLAN/2, Digital Audio/Video Broadcasting (DAB/DVB), and for 4G Radio mobile communications. This is because of its high bandwidth efficiency as the use of orthogonal waveforms with overlapping spectra. The immunity to multipath fading channel and the capability for parallel signal processing make it a promising candidate for the next generation mobile communication systems. The modulation and demodulation of OFDM based communication systems can be efficiently implemented with an FFT and IFFT, which has made the FFT valuable for those communication systems. The complexity of an OFDM system highly depends upon the computation of Fast Fourier Transform (FFT) algorithm. With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well-known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day.

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