Performance analysis of a two-level carry-skip adder implemented in complementary pass-transistor logic

Abstract

Performance evaluation of a two-level carry-skip adder using complementary pass-transistor logic (CPL) is presented in this paper. The adder is compared with a full-CMOS version of the two-level carry-skip architecture, with a carry-lookahead adder automatically generated with ALLIANCE CAD tools and with a recently proposed 32-bit carry-select adder. Furthermore, performances of a single-level carry-skip adder implemented in CPL. are investigated. These comparisons are carried out in order to evaluate the impact of the architecture and of the logic style on the performances. SPICE simulations of the circuit extracted from the layout, including parasitics, are used to evaluate the adders delay, while switch-level simulations are used to evaluate the average power dissipation. The proposed two-level carry-skip CPL adder is fast, area efficient and highly modular.