Abstract
PCI Express (PCIe) specification has been doubling the data rate every generation in a backward compatible manner every two to three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. We propose a new flit-based approach with a lightweight, low-latency FEC coupled with a strong cyclic redundancy check (CRC) and a low-latency link-level retry mechanism to meet the stringent low-latency, high-bandwidth, and high-reliability goals. We also present a new low-power state that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow.
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