PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect

Abstract

PCI Express® (PCIe®) specification doubles the data rate every generation in a backwards compatible manner every three years. With PCIe 6.0 specification at 64.0 GT/s, we will be adopting PAM-4 signaling to ensure the channel reach remains the same as PCIe 5.0 specification at 32.0 GT/s. PAM-4 requires a Forward Error Correction (FEC) mechanism due to the high BER. However, since PCIe technology is a Load-Store architecture, the latency adder due to FEC must be less than 10ns and ideally 0. We present the new flit-based approach with a light-weight low-latency FEC coupled with a low-latency link level retry mechanism. We demonstrate that PCIe 6.0 architecture improves the bandwidth efficiency in the range of 0.95 to 1.4, resulting in a net bandwidth increase of 1.9X to 2.8X, depending on the payload size of the packets, in spite of the FEC and CRC overheads. The latency also decreases in most cases. The reliability (FIT) of our approach is demonstrated to less than 10−9. We also present a new power savings strategy that results in power consumption proportional to bandwidth usage without impacting the traffic flow.