Patterning strategy for low-K 1 lithography

Abstract

Moore's law has been guiding the semiconductor industry for four decades. Lithography is the key enabler to keep the industry on the technology treadmill. Lithographers have been facing unprecedented challenges during last five years to keep the technology on the technology treadmill by developing various kinds of resolution enhancement techniques (RETs). In low K1 regime, co-optimization of design, layout mask, OPC, lithography and etching is the primary strategy to deliver a production-worthy patterning solution. Optical shrink is not a trivial task anymore. Intel always pursues parallel patterning techniques based on the dual exposure wavelength patterning strategy. While EUVL is the preferred patterning solution for 32nm node, 193nm immersion lithography with super high NA illumination is one of the parallel patterning strategies. The effects of polarization at super high NA illumination on mask technology, such as lens reduction ratio, blank absorber thickness and image imbalance correction, and restriction on design layout are addressed in this paper. Contact patterning is extremely challenging at low K1. Contact shape factor (circularity) which impacts the design rule will be discussed in this paper. Explosion of data file size and mask write time, stringent mask CD control and mask defect disposition are direct consequences of low-K1/high-MEEF (Mask Error Enhancement Factor) lithography. Mask makers alone cannot resolve the challenges in a cost effective manner. A seamless integration solution is a must.