Patterning of silicon nitride for CMOS gate spacer technology. I. Mechanisms involved in the silicon consumption in CH3F/O2/He high density plasmas

Abstract

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.