Patterning of 32 nm 1:1 Line and Space by Resist Reflow Process

Abstract

Producing a sub-32 nm line and space pattern is one of the most important issues in semiconductor manufacturing. In particular, it is important to produce line and space patterns in flash memory-type devices because the unit cell is mostly composed of line and space patterns. The double patterning method is regarded as the most promising technology for producing a sub-32 nm half-pitch node. However, the double patterning method is expensive for the production and a heavy data split is required. In order to achieve cheaper and easier patterning, we propose a resist reflow process (RRP) for producing 32 nm 1:1 line and space patterns. In many cases, it is easier to produce a 1:3 pitch line and space pattern than a 1:1 pitch line and space pattern in terms of the aerial image, and RRP can transform a 1:3 pitch aerial image to a 1:1 resist image. We used a home-made RRP simulation based on the Navier–Stokes equation including the surface tension effect. Solid-E of Synopsis is used for the optical simulation, and electron-beam lithography is used for the experiment to verify the concept.