Abstract
In this paper, a new BIST structure is presented, which is generated by the LFSR modified. There is no redundant single input jump test incentive, all possible test vector combinations are covered, the testing power is reduced. Moreover, the testing time do not increase and fault-coverage rate won't be affected. Experiment results on the integrated circuit 74HC42 show that the switching activity reduction can be achieved up to 64% while achieving high fault coverage, especially suitable for BIST of Integrated circuits.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
