Abstract
We review the prevailing causes of and remedies for profile distortion (notching) resulting from pattern-dependent charging during etching in high density plasmas. A new mechanism for notch reduction, based on electron tunneling through thin gate oxides, is explained through detailed modeling and simulations of charging and profile evolution in polysilicon gate definition. Tunneling currents from the substrate decrease surface charging potentials–responsible for ion deflection–at the bottom of high aspect ratio trenches. The exponential dependence of electron tunneling on the oxide electric field predicts an abrupt transition from severe notching to virtually no notching as the gate oxide thickness is decreased, which has been seen in experiments.
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