Path Delay Fault Simulation on Large Industrial Designs

Abstract

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay fault simulation is more expensive than stuck-at fault simulation, our experiments show that performance of path delay fault grading is comparable to that of stuck-at fault grading. Finally, we propose and evaluate a heuristic that can improve path delay fault simulation performance and also aid in selection of tests for speed-limiting paths.