Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units

Abstract

Multi/many-core processors allow to handle path delay faults although the number of paths exponentially grows with the circuit size. This paper proposes an efficient path delay fault simulation that identifies all the robust and non-robust testable path delay faults for each test pattern. The simulation result is expressed by a scalable data structure only proportional to the numbers of gates and test patterns. The proposed simulation uses two types of parallelism, bit- and thread-parallelism, while considering efficient usage of multiple computing units and SIMD units which is resulting in a very fast simulation. Experimental results demonstrate the efficiency of the proposed method identifying all the robust and non-robust testable paths for a large number of test patterns. In addition, the simulation surpasses a commercial logic simulator which just processes a part of the proposed method.